Serializer/deserializer (SERDES) integrated circuits are commonly used in electronic systems where there is a need for transporting large amounts of data at high speed between two slow speed systems. SERDES integrated circuits have a wide range of applications from personal computer (PC) motherboards to cellular mobile base stations. Such applications sometimes demand precise knowledge of the propagation delay that results from transporting the data between two modules.
A SERDES integrated circuit (or “SERDES chip”) can transport large amounts of data at high speed within an electronic system. A SERDES chip is typically used to transport data across a board or a backplane. A SERDES chip usually has two input/output (I/O) interfaces. One of the I/O interfaces is a low speed, parallel bus interface that sends and receives data bits from other components (e.g., application specific integrated circuits (ASICs) or microprocessors). The other I/O interface operates at high speed and sends and receives data through a serial line that usually comprises a pair of wires or signal traces on a board.
FIG. 1 illustrates a schematic diagram of a prior art SERDES chip 100. The transmitter (TX) 105 of SERDES chip 100 shown in FIG. 1 receives data from a low speed N-bit parallel input bus 110. The SERDES chip 100 converts the low speed parallel N-bits into a serial data stream. The transmitter 105 of the SERDES chip 100 then transmits the serial data stream on a high-speed serial output bus 115.
The receiver (RX) 120 of SERDES chip 100 also receives data from a high-speed serial input bus 125. The SERDES chip 100 converts the high-speed serial data into a N-bit parallel data stream. The receiver 120 of the SERDES chip 100 then outputs the parallel data stream on a low speed N-bit parallel output bus 130.
FIG. 2 illustrates how two prior art SERDES chips (220 and 230) may employed in a cellular mobile base station 200. The control system 210 of the base station 200 processes the data and sends the data through a low speed parallel bus 215 to the parallel input of SERDES chip 220. The SERDES chip 220 serializes the data and then transmits the data at high speed through transmission medium 225 to the remote SERDES chip 230. The remote SERDES chip 230 deserializes the data and sends the deserialized data to the remote system 240 on a low speed N-bit parallel output bus 235. The remote system 240 then sends the data to radio tower 245.
Similarly, the remote system 240 of the base station 200 processes data and sends the data through a low speed parallel input bus 250 to the parallel input of remote SERDES chip 230. The remote SERDES chip 230 serializes the data and then transmits the serialized data at high speed through transmission medium 255 to the SERDES chip 220. The SERDES chip 220 deserializes the data and sends the deserialized data to the control system 210 on a low speed N-bit parallel output bus 260.
The transmission medium (225 and 255) between SERDES chip 220 and SERDES chip 230 could be an electrical link in the form of a pair of signal traces on a board or a cable going from board to board. The transmission medium (225 and 255) could also be an optical link in a case in which the SERDES signals go to the input of an optical transceiver that converts the electrical signals to optical signals for transmission to the remote system.
In a SERDES system of the type shown in FIG. 2 the system operator is often interested in acquiring a precise measurement of the data propagation delay between the control system 210 and the remote system 240. To obtain this information it is necessary to know the data propagation delay in the SERDES chips (220 and 230). In a SERDES chip there are a number of propagation delays that are of interest to a system operator. Consider, for example, the data propagation delays in the SERDES chip 220 illustrated in FIG. 3.
The data propagation delay that is denoted TPS refers to the delay from the parallel input bus 215 to the serial output transmission medium 225. The data propagation delay that is denoted TSS refers to the delay from the serial output transmission medium 225 to the serial input transmission medium 255. The data propagation delay that is denoted TSP refers to the delay from the serial input transmission medium 255 to the parallel output bus 260. The data propagation delay that is denoted TPP refers to the delay from the parallel input bus 215 to the parallel output bus 260.
The measurements (TPS TSS TSP TPP) allow the control system 210 to measure the data propagation delay not only across the SERDES chip 220 but also across other components in the system. This is accomplished by taking advantage of several loop-back capabilities that are available within SERDES chips and within the system in general. A SERDES chip is capable of looping back data along the TPP path, the TSS path, the TPS-TSS-TSP path, and the TSP-TPP-TPS path. The TSP-TPP-TPS path is not shown in FIG. 3. By utilizing the loop-back modes and the data propagation delay measurements, control system 210 can estimate such things as data propagation delay across the transmission medium (225 and 255) between SERDES chip 220 and SERDES chip 230, the data propagation delay through SERDES chip 220, the data propagation delay through SERDES chip 230, and the data propagation delay through the remote system 240.
FIG. 4 illustrates an exemplary transmit data path within a prior art SERDES chip. A signal conditioning unit 410 of the transmitter portion of the SERDES chip receives data from a low speed N-bit parallel input bus. The data is then passed to a synchronizer (first in first out (FIFO)) unit 420. The synchronized data is then encoded in encoder 430 and passed to synchronizer (first in first out (FIFO)) unit 440. The parallel data is then serialized in serializer unit 450. The serial data is then transmitted by high-speed transmitter 460.
As shown in FIG. 4, the synchronizer (FIFO) unit 420 bridges input low speed clock domain 470 and internal low speed clock domain 480. The synchronizer (FIFO) unit 440 bridges internal low speed clock domain 480 and low speed serializer clock domain 490. Serializer unit 450 bridges low speed serializer clock domain 490 and high-speed transmitter clock domain 495.
FIG. 5 illustrates an exemplary receive data path within a prior art SERDES integrated circuit chip. An equalizer unit 510 of the receiver portion of the SERDES chip receives data from a high-speed serial input bus. The data is then passed to a clock and data recovery unit 520. The serial data is then deserialized in deserializer unit 530. The data is then decoded in decoder unit 540. The data is then passed to synchronizer (first in first out (FIFO)) unit 550. The synchronized data is then passed to signal conditioning unit 560. The data is then output from signal conditioning unit 560 to a low speed N-bit parallel output bus.
As shown in FIG. 5, the deserializer unit 530 bridges high-speed receiver clock domain 570 and internal low speed clock domain 580. The synchronizer (first in first out (FIFO)) unit 550 bridges internal low speed clock domain 580 and output low speed clock domain 590.
FIG. 4 shows that there are multiple clock domains (470, 480, 490, 495) along the transmit data path. FIG. 5 shows that there are multiple clock domains (570, 580, 590) along the receive data path. These multiple clock domains have different frequencies and have arbitrary phase relationships with respect to each other. The presence of multiple clock domains complicates the process of accurately measuring the data propagation delay in a SERDES chip.
In addition, the synchronizer (FIFO) units have delays that may vary depending upon operating conditions. That is, there are certain delays in a SERDES chip that can vary over time. It is also rather difficult to measure the precise data propagation delay of data packets that are being converted from the parallel domain to the serial domain (or from the serial domain to the parallel domain). These factors complicate the measurement of data propagation delay in a SERDES chip.
Some attempts have been made in the prior art to quantify the data propagation delay across a SERDES chip. The major difficulty lies in measuring the data propagation delay between the parallel side and the serial side of the SERDES chip. This difficulty stems from (1) the large difference in the two data rates (low speed versus high speed), and (2) the difference in data format (serial versus parallel) at the two ends, and (3) the multiple clock domains through which the data passes. For these reasons prior art measurement attempts have generally focused on measuring the data propagation delay for elements that do not convert the data format from parallel to serial (or from serial to parallel).
One prior art approach has been to measure the data propagation delay across the synchronizer (FIFO) units. The synchronizer (FIFO) units synchronize data transfer between the different clock domains in a SERDES chip. The first in first out (FIFO) data propagation delay depends on the phase and frequency difference between the two clock domains that are straddled by a synchronizer (FIFO) unit. This makes the data propagation delay across a synchronizer (FIFO) unit inherently ambiguous.
The data propagation delay across the synchronizer (FIFO) units can account for a significant part of the total data propagation delay within a SERDES chip. The prior art method that is used to measure the data propagation delay across the synchronizer (FIFO) units uses a counter that detects the time that it takes certain characters in the bit stream to travel from the input to the output. This approach suffers from the inherent disadvantage of not being able to account for the total data propagation delay across the SERDES chip. Because the data propagation delay across the synchronizer (FIFO) units does not account for the total data propagation delay within the SERDES chip, the measurement of the data propagation delay across the synchronizer (FIFO) units is at best only an approximation of the total data propagation delay within the SERDES chip.
In order to overcome the limitations that are involved in measuring only the data propagation delay across the synchronizer (FIFO) units, other prior art methods have used external application specific integrated circuits (ASICs) to measure the data propagation delay across a SERDES chip. The ASIC chips typically run at a fraction of the speed of a SERDES chip. This means that an ASIC chip has to rely on measuring the round trip time through a SERDES chip with both the input and the output being accessed from the parallel side.
This method has two limitations. The first limitation is that the data propagation delay may not be symmetrical along the parallel-to-serial path and the serial-to-parallel path in a SERDES chip. That is, the delay along the parallel-to-serial path may not be equal to the delay along the serial-to-parallel path. An ASIC chip will not be able to decouple the delay across one of the paths from the delay across the other of the two paths.
The second limitation is that the ASIC chip has a slow clock speed. The accuracy of the delay measurement is primarily determined by the clock speed of the measuring device. This means that the ASIC chip method is limited to low accuracy. The ASIC chip method may therefore be unsuitable for certain applications such as applications in the cellular base station market.
Therefore, there is a need in the art for an improved system and method for making highly accurate data propagation delay measurements in a SERDES integrated circuit.